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1 ? fn9135.3 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003-2004. all rights reserved. dynamic vid? is a registered trademark of intersil americas i nc. all other trademarks mentioned are the property of their respective owners. isl6565a, ISL6565B multi-phase pwm controller with precision r ds(on) or dcr current sensing for vr10.x application the isl6565a, ISL6565B controls microprocessor core voltage regulation by driving up to 3 synchronous-rectified buck channels in parallel. multi-phase buck converter architecture uses interleaved timing to multiply channel ripple frequency and reduce input and output ripple currents. the difference between the isl6565a and the ISL6565B is that the isl6565a utilizes r ds(on) current sensing, while the ISL6565B utilizes dcr current sensing for each phase. these cost and space saving methods of current sensing are used for adaptive voltage positioning (droop), channel- current balancing, and overcurrent protection. to ensure the accuracy of droop, a programmable internal temperature compensation function is im plemented to compensate the effect of r ds(on) and dcr temperature sensitivity. a unity gain, differential amplifier is provided for remote voltage sensing. any potential difference between remote and local grounds is eliminated using the remote-sense amplifier. the precision thresh old-sensitive enable input is available to accurately coordinate the start up of the isl6565a, ISL6565B with intersil mosfet driver ics. dynamic-vid? technology allows seamless on-the-fly vid changes. the offset pin allows accurate voltage offset settings that are independent of vid setting. features ? multi-phase power conversion - 2 or 3 phase operation ? precision core voltage regulation - differential remote voltage sensing - 0.5% system accuracy over temperature and life - adjustable reference-voltage offset ? precision r ds(on) or dcr current sensing - integrated programmable temperature compensation - accurate load-line programming - accurate channel-current balancing - low-cost, lossless current sensing ? input voltage: 12v or 5v bias ? microprocessor voltag e identification input - dynamic vid? technology - 6-bit vid input - 0.8375v to 1.600v in 12.5mv steps ? threshold enable function for precision sequencing ? overcurrent protection ? overvoltage protection ? digital soft-start ? operation frequency up to 1.5mhz per phase ? qfn package - compliant to jedec pub95 mo-220 qfn - quad flat no leads - package outline - near chip scale package footprint, which improves pcb efficiency and has a thinner profile ? pb-free available ordering information part number temp. (c) package pkg. dwg. # isl6565acb 0 to 105 28 ld soic m28.3 isl6565acbz (note) 0 to 105 28 ld soic (pb-free) m28.3 isl6565acr 0 to 105 28 ld 5x5 qfn l28.5x5 isl6565acrz (note) 0 to 105 28 ld 5x5 qfn (pb-free) l28.5x5 isl6565acv 0 to 105 28 ld tssop m28.173 isl6565acvz (note) 0 to 105 28 ld tssop (pb-free) m28.173 ISL6565Bcb 0 to 105 28 ld soic m28.3 ISL6565Bcbz (note) 0 to 105 28 ld soic (pb-free) m28.3 ISL6565Bcr 0 to 105 28 ld 5x5 qfn l28.5x5 ISL6565Bcrz (note) 0 to 105 28 ld 5x5 qfn (pb-free) l28.5x5 ISL6565Bcv 0 to 105 28 ld tssop m28.173 ISL6565Bcvz (note) 0 to 105 28 ld tssop (pb-free) m28.173 note: intersil pb-free products em ploy special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow te mperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020b. data sheet september 2004
2 pinouts isl6565acb (soic), isl6565acv (tssop) top view isl6565acr (qfn) top view ISL6565Bcb (soic), ISL6565Bcv (tssop) top view ISL6565Bcr (qfn) top view fs en vcc enll nc isen2 pwm2 pwm1 isen1 isen3 pwm3 gnd rgnd vsen ovp pgood vid4 vid3 vid2 vid1 vid0 vid12.5 ofs tcomp ref fb comp vdiff 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 vid4 pgood ovp fs en vcc enll nc isen2 pwm2 pwm1 isen1 isen3 pwm3 ref fb comp vdiff vsen rgnd gnd vid3 vid2 vid1 vid0 vid12.5 ofs tcomp 1 2 3 4 5 6 7 21 20 19 18 17 16 15 28 27 26 25 24 23 22 8 9 10 11 12 13 14 fs en vcc enll icommon isen2 pwm2 pwm1 isen1 isen3 pwm3 gnd rgnd vsen ovp pgood vid4 vid3 vid2 vid1 vid0 vid12.5 ofs tcomp ref fb comp vdiff 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 vid4 pgood ovp fs en vcc enll icommon isen2 pwm2 pwm1 isen1 isen3 pwm3 ref fb c omp v diff v sen r gnd gnd vid3 vid2 vid1 vid0 vid12.5 ofs tcomp 1 2 3 4 5 6 7 21 20 19 18 17 16 15 28 27 26 25 24 23 22 8 9 10 11 12 13 14 isl6565a, ISL6565B
3 isl6565a block diagram i_trip ovp latch channel shunt regulator pwm1 pwm2 pwm3 gnd vcc fb fs s clock and comp vsen generator sawtooth isen3 rgnd vdiff pgood ovp en 1.24v channel current balance channel detect ofs isen1 isen2 channel current sense ovp soft-start and fault logic +200mv r x1 e/a oc pwm pwm q tcomp enll nc uvp x 0.75 vid4 vid3 vid2 vid1 vid0 dynamic vid d/a vid12.5 ref pwm power-on reset temp comp ocp 1 n i_avg offset isl6565a, ISL6565B
4 ISL6565B block diagram i_trip ovp latch channel shunt regulator pwm1 pwm2 pwm3 gnd vcc fb fs s clock and comp vsen generator sawtooth isen3 rgnd vdiff pgood ovp en 1.24v channel current balance channel detect ofs isen1 isen2 channel current sense ovp soft-start and fault logic +200mv r x1 e/a oc pwm pwm q tcomp enll uvp x 0.75 vid4 vid3 vid2 vid1 vid0 dynamic vid d/a vid12.5 ref pwm power-on reset temp comp ocp 1 n i_avg offset icommon isl6565a, ISL6565B
5 typical application - isl6565a vid3 +5v +5v vin vid4 pgood vid2 vid1 vid0 vsen vdiff fb comp vcc gnd rgnd isen1 pwm1 pwm2 isen2 pwm3 isen3 isl6565a p load vid12.5 enll ovp fs ofs tcomp en ref +12v r t nc +5v vin pwm vcc boot ugate phase en lgate gnd isl6605 +5v vin vid_pgood pwm vcc boot ugate phase en lgate gnd isl6605 pwm vcc boot ugate phase en lgate gnd isl6605 isl6565a, ISL6565B
6 typical application - ISL6565B vid3 +5v +5v vin vid4 pgood vid2 vid1 vid0 vsen vdiff fb comp vcc gnd rgnd isen1 pwm1 pwm2 isen2 pwm3 isen3 ISL6565B p load vid12.5 enll ovp fs ofs tcomp en ref +12v r t icommon +5v vin +5v vin vid_pgood pwm vcc boot ugate phase en lgate gnd isl6605 pwm vcc boot ugate phase en lgate gnd isl6605 pwm vcc boot ugate phase en lgate gnd isl6605 isl6565a, ISL6565B
7 absolute m aximum ratings supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7v input, output, or i/o voltage (except ovp) . .gnd -0.3v to v cc + 0.3v ovp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15v esd (human body model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>4kv esd (machine model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>300v esd (charged device model) . . . . . . . . . . . . . . . . . . . . . . . . . .>2kv operating conditions supply voltage, vcc (5v bias mode) . . . . . . . . . . . . . . . . +5v 5% junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . 0c to 125c thermal information thermal resistance ja (c/w) jc (c/w) soic package (note 1) . . . . . . . . . . . . 62 n/a qfn package (notes 2, 3). . . . . . . . . . 33 3.5 tssop package (note 1) . . . . . . . . . . 85 n/a maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150c maximum storage temperature range . . . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300c (soic - lead tips only) caution: stress above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress onl y rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. notes: 1. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. 2. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 3. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications operating conditions: vcc = 5v or icc < 25ma (note 3), t j = 0c to 105c. unless otherwise specified. parameter test conditions min typ max units vcc supply current nominal supply vcc = 5vdc; en = 5vdc; r t = 100k ?, isen1 = isen2 = isen3 = -70 a -1418ma shutdown supply vcc = 5vdc; en = 0vdc; r t = 100k ? -1014ma shunt regulator vcc voltage vcc tied to 12vdc thru 300 ? resistor, r t = 100k ? 5.6 5.9 6.2 v vcc sink current vcc tied to 12vdc thru 300 ? resistor, r t = 100k ? --25ma power-on reset and enable por threshold vcc rising 4.2 4.31 4.50 v vcc falling 3.7 3.82 4.00 v enable threshold en rising 1.29 1.31 1.33 v hysteresis - 150 - mv fault reset 1.10 1.14 1.18 v enll input logic low level --0.4v enll input logic high level 0.8 - - v enll leakage current enll = 5v - - 1 a reference voltage and dac system accuracy (vid = 1.2v-1.6v, t j = 0c to 85c) -0.5 - 0.5 %vid system accuracy (vid = 0.8375v-1.1875v t j = 25c) -0.7 - 0.7 %vid system accuracy (vid = 0.8375v-1.1875v, t j = 0c to 85c) -0.8 - 0.8 %vid vid pull up -65 -50 -35 a vid input low level --0.4v vid input high level 0.8 - - v dac source/sink current vid = 010100 -200 - 200 a ref source/sink current -50 - 50 a pin-adjustable offset voltage at ofs pin offset resistor connected to ground 485 500 515 mv voltage below vcc, offset resistor connected to vcc 1.97 2.03 2.09 v isl6565a, ISL6565B
8 oscillator accuracy r t = 100k ? -10 - 10 % adjustment range 0.08 - 1.5 mhz sawtooth amplitude -1.5- v max duty cycle - 66.7 - % error amplifier open-loop gain r l = 10k ? to ground - 80 - db open-loop bandwidth c l = 100pf, r l = 10k ? to ground - 18 - mhz slew rate c l = 100pf 4.5 6.0 7.5 v/ s maximum output voltage 4.0 4.3 - v output high voltage @ 2ma 3.7 - - v output low voltage @ 2ma - - 1.35 v remote-sense amplifier bandwidth -20-mhz output high current vsen - rgnd = 2.5v -500 - 500 a output high current vsen - rgnd = 0.6 -500 - 500 a pwm output pwm output voltage low threshold iload = 500 a--0.3v pwm output voltage high threshold iload = 500 a4.3--v temperature compensation temperature compensation current @ 40c and tcomp = 0.5v 10 15 20 a temperature compensation transconductance - 2 - a/v / c sense current sensed current tolerance isen1 = isen2 = isen3 = 80 a, 0c to 105c 74 81 91 a overcurrent trip level 95 110 130 a power good and protection monitors pgood low voltage i pgood = 4ma - - 0.4 v undervoltage offset from vid vsen falling 72 74 76 %vid overvoltage threshold voltage above vid, after soft-start (note 6) 180 200 220 mv before enable - 1.63 - v vcc < por threshold 1.7 1.8 1.87 v overvoltage reset voltage vcc por threshold, vsen falling - 0.6 - v vcc < por threshold - 1.5 - v ovp drive voltage i ovp = -100ma, vcc = 5v - 1.9 - v minimum vcc for ovp 1.4 - - v notes: 4. when using the internal shunt regulat or, vcc is clamped to 6.02v (max). cu rrent must be limited to 25ma or less. 5. these parts are designed and adjusted for accuracy with all errors in the voltage loop included. 6. during soft-start, vdac rises from 0 to vid. the over voltage trip level is the higher of 1.7v and vdac + 0.2v. electrical specifications operating conditions: vcc = 5v or icc < 25ma (note 3), t j = 0c to 105c. unless otherwise specified. (continued) parameter test conditions min typ max units isl6565a, ISL6565B
9 functional pin description vcc - supplies all the power necessary to operate the chip. the controller starts to operate when the voltage on this pin exceeds the rising por threshold and shuts down when the voltage on this pin drops below the falling por threshold. connect this pin directly to a +5v supply or through a series 300 ? resistor to a +12v supply. gnd - bias and reference ground for the ic. en - this pin is a threshold-sensitive enable input for the controller. connecting the 12v supply to en through an appropriate resistor divider provides a means to synchronize power-up of the controller and the mosfet driver ics. when en is driven above 1.31v, the isl6565a, ISL6565B is active depending on status of enll, the internal por, and pending fault states. driving en below 1.14v will clear all fault states and prime the isl6565a, ISL6565B to soft-start when re-enabled. enll - this pin is a logic-level enable input for the controller. when asserted to a logic high, the isl6565 is active depending on status of en, the internal por, vid inputs and pending fault states. deasserting enll will clear all fault states and prime the isl6565a, ISL6565B to soft- start when re-enabled. fs - a resistor, placed from fs to ground, will set the switching frequency. refer to equation 45 for proper resistor calculation. vid4, vid3, vid2, vid1 , vid0, and vid12.5 - these are the inputs to the internal dac that provides the reference voltage for output regulation. connect these pins either to open-drain outputs with or without external pull-up resistors or to active-pull-up outputs. vid4-vid12.5 have 20 a internal pull-up current sources that diminish to zero as the voltage rises above the logic-high level. vdiff, vsen, and rgnd - vsen and rgnd are inputs to the precision differential re mote-sense amplifier. this amplifier converts the differential voltage of the remote output to a single-ended voltage referenced to local ground. vdiff is the amplifier?s output and the input to the regulation and protection circuitry. connect vsen and rgnd to the sense pins of the remote load. fb and comp - inverting input and output of the error amplifier respectively. fb is connected to vdiff through a resistor. a negative current, proportional to output current is present on the fb pin. a prop erly sized resistor between vdiff and fb sets the load line (droop). the droop scale factor is set by the ratio of the isen resistors and the lower mosfet r ds(on) or inductor dcr. comp is tied back to fb through an external r-c network to compensate the regulator. ref - the ref input pin is the positive input of the error amp. it is internally connected to the dac output through a 1k ? resistor. a capacitor is used between the ref pin and ground to smooth the voltage transition during dynamic vid? operations. tcomp - temperature compensation scaling input. a resistor from this pin to ground sets the gain of the internal thermal sense circuitry. the temperature sensed by the controller is utilized to modify the droop current output to the fb pin, adjusting for mosfet r ds(on) and inductor dcr variations with temperature. pwm1, pwm2, pwm3 - pulse-width modulation outputs. connect these pins to the pwm input pins of the intersil driver ics. the number of active channels is determined by the state of pwm3. tie pwm3 to vcc to configure for 2-phase operation. isen1, isen2, isen3, ic ommon (ISL6565B only) - these pins are used for sensing individual phase output currents. the sensed current is used for channel balancing, protection, and load line regulation. isen3 should be left open for 2-phase operation. for r ds(on) current sensing using the isl6565a, connect a resistor between the isen1, isen2, and isen3 pins and their respective phase node. this resistor sets a current proportional to the current in the lower mosfet during it?s conduction interval. for dcr sensing using the ISL6565B, connect a resistor from vcore to the icommon pin. then connect isen1, isen2, and isen3 to the node between the rc sense elements surrounding the inductor of their respective phase. pgood - pgood is used as an indication of the end of soft-start. it is an open-drain logic output that is low impedance until the soft-start is completed. it will be pulled low again once the undervoltage point is reached. ofs - the ofs pin provides a means to program a dc current for generating an offset voltage across the droop resistor between fb and vdiff. the offset current is generated via an external resistor and precision internal voltage references. the polarity of the offset is selected by connecting the resistor to gnd or vcc. for no offset, the ofs pin should be left unconnected. ovp - overvoltage protection pin. this is an open drain device, which can be externally configured with a resistor to control an scr to shut down the regulator. isl6565a, ISL6565B
10 operation multi-phase power conversion microprocessor load current pr ofiles have changed to the point that the advantages of multi-phase power conversion are impossible to ignore. the technical challenges associated with producing a single-phase converter that is both cost-effective and thermally viable have forced a change to the cost-saving appr oach of multi-phase. the isl6565a, ISL6565B controller helps simplify implementation by integrating vital functions and requiring minimal output components. the block diagrams on pages 2 and 3 provide top level views of multi-phase power conversion using the isl6565a and ISL6565B controllers. interleaving the switching of each channel in a multi-phase converter is timed to be symmetrically out of phase with each of the other channels. in a 3-phase converte r, each channel switches 1/3 cycle after the previous chann el and 1/3 cycle before the following channel. as a result, the three-phase converter has a combined ripple frequency three times greater than the ripple frequency of any one phas e. in addition, the peak-to- peak amplitude of the combined inductor currents is reduced in proportion to the number of phases (equations 1 and 2). increased ripple frequency and lower ripple amplitude mean that the designer can use less per-channel inductance and lower total output capacitance for any performance specification. figure 1 illustrates the multiplica tive effect on output ripple frequency. the three channel currents (il1, il2, and il3) combine to form the ac ripple current and the dc load current. the ripple component has three times the ripple frequency of each individual channel current. each pwm pulse is terminated 1/3 of a cycle after the pwm pulse of the previous phase. the peak-to- peak current for each phase is about 7a, and the dc components of the inductor currents combine to feed the load. to understand the reduction of ripple current amplitude in the multi-phase circuit, examine the equation representing an individual channel?s peak-to-peak inductor current. in equation 1, v in and v out are the input and output voltages respectively, l is the single-channel inductor value, and f s is the switching frequency. the output capacitors conduct the ripple component of the inductor current. in the case of multi-phase converters, the capacitor current is the sum of the ripple currents from each of the individual channels. compare equation 1 to the expression for the peak-to-peak current after the summation of n symmetrically phase-shifted inductor currents in equation 2. peak-to-peak ripple current decreases by an amount proportional to the number of channels. output- voltage ripple is a function of capacitance, capacitor equivalent series resistance (esr), and inductor ripple current. reducing the inductor ripple current allows the designer to use fewer or less costly output capacitors. another benefit of interleaving is to reduce input ripple current. input capacitance is determined in part by the maximum input ripple current. multi-phase topologies can improve overall system cost and size by lowering input ripple current and allowing the designer to reduce the cost of input capacitance. the example in figure 2 illustrates input currents from a three-phase converter combining to reduce the total input ripple current. the converter depicted in figure 2 delivers 1.5v to a 36a load from a 12v input. the rms input capacitor current is 5.9a. compare this to a single-phase converter also stepping down 12v to 1.5v at 36a. the si ngle-phase converter has 11.9a rms input capacitor current. the single-phase converter must use an input capacitor bank with twice the rms current capacity as the equivalent three-phase converter. figure 1. pwm and inductor-current waveforms for 3-phase converter 1 s/div pwm2, 5v/div pwm1, 5v/div il2, 7a/div il1, 7a/div il1 + il2 + il3, 7a/div il3, 7a/div pwm3, 5v/div i pp v in v out ? () v out lf s v in ----------------------------------------------------- - = (eq. 1) i cpp , v in nv out ? () v out lf s v in ----------------------------------------------------------- - = (eq. 2) figure 2. channel input currents and input- capacitor rms current for 3-phase converter channel 1 input current 10a/div channel 2 input current 10a/div channel 3 input current 10a/div input-capacitor current, 10a/div 1 s/div isl6565a, ISL6565B
11 figures 19 and 20 in the section entitled input capacitor selection can be used to determine the input-capacitor rms current based on load current, duty cycle, and th e number of channels. they are provided as aids in determining the optimal input capacitor solution. pwm operation the timing of each converter leg is set by the number of active channels. the default channel setting for the isl6565a, ISL6565B is three. one switching cycle is defined as the time between pwm1 pulse termination signals. the pulse termination signal is the internally generated clock signal that triggers the falling edge of pwm1. the cycle time of the pulse termination signal is the inverse of the switching frequency set by the resistor between the fs pin and ground. each cycle begins when the clock signal commands pwm1 to go low. the pwm1 transition signals the channel-1 mosfet driver to turn off the channel-1 upper mosfet and turn on the channel-1 synchronous mosfet. in the default channel configuration, the pwm2 pulse terminates 1/3 of a cycle after the pwm1 pulse. the pwm3 pulse terminates 1/3 of a cycle after pwm2. if pwm3 is connected to v cc, two channel operation is selected and the pw m2 pulse terminates 1/2 of a cycle after the pwm1 pulse terminates. once a pwm pulse transitions low, it is held low for a minimum of 1/3 cycle. this forc ed off time is required to ensure an accurate current sample. current sensing is described in the next section. after the forced off time expires, the pwm output is enabled. the pwm output state is driven by the position of t he error amplifier output signal, v comp , minus the current correction signal relative to the sawtooth ramp as illustrated in figure 6. when the modified v comp voltage crosses the sawtooth ramp, the pwm output transitions high. the mosfet driver detects the change in state of the pwm signal and turns off the synchronous mosfet and turns on the upper mosfet. the pwm signal will remain high until the pulse termination signal marks the beginning of the next cycle by tr iggering the pwm signal low. current sampling during the forced off-time, following a pwm transition low, the current-sense amplifier uses the isen inputs to reproduce a signal proportional to the inductor current, i l . no matter which current-sens e method is employed, the sense current (i sen ) is simply a scaled version of the inductor current. the sample window opens exactly 1/6 of the switching period, t sw , after the pwm transitions low. the sample window then stays open for a fixed amount of time, t sample , and is equal to 1/6 of the switching period, t sw as illustrated in figure 3. the sampled current, at the end of the t sample , is proportional to the inductor current and is held until the next switching period sample. the sampled current is used for current balance, load-line regulation, and overcurrent protection. current sensing the isl6565a supports mosfet r ds(on) current sensing, while the ISL6565B supports inductor dcr current sensing. the internal circuitry, shown in figures 4 and 5, represent channel n of an n-channel converter. this circuitry is repeated for each channel in the converter, but may not be active depending on the status of the pwm3 pin, as described in the pwm operation section. mosfet r ds(on) sensing (isl6565a only) the isl6565a senses the channel load current by sampling the voltage across the lower mosfet r ds(on) , as shown in figure 4. a ground-referenced operational amplifier, internal to the isl6565a, is connected to the phase node through a resistor, r isen . the voltage across r isen is equivalent to the voltage drop across the r ds(on) of the lower mosfet while it is conducting. the resu lting current into the isen pin is proportional to the channel current, i l . the isen current is sampled and held as described in the current sampling section. from figure 4, the following equation for i n is derived where i l is the channel current. t sample t sw 6 ---------- 1 6f sw ? ------------------ == (eq. 3) figure 3. sample and hold timing time pwm i l i sen new sample current t sample switching period old sample current i n i l r ds on () r isen ---------------------- = (eq. 4) isl6565a, ISL6565B
12 inductor dcr sensing (ISL6565B only) inductor windings have a characteristic distributed resistance or dcr (direct current resistance). for simplicity, the inductor dcr is considered as a separate lumped quantity, as shown in figure 5. the channel current i l , flowing through the inductor, passes through the dcr. equation 5 shows the s-domain equivalent voltage, v l , across the inductor. a simple r-c network across the inductor (r 1 and c) extracts the dcr voltage, as shown in figure 5. the voltage across the sense capacitor, v c , can be shown to be proportional to the channel current i l , shown in equation 6. in some cases it may be necessa ry to use a resistor divider r-c network to sense the current through the inductor. this can be accomplished by placing a second resistor, r 2 , across the sense capacitor. in these cases the voltage across the sense capacitor, v c , becomes proportional to the channel current i l , and the resistor divider ratio, k. if the r-c network components are selected such that the rc time constant matches the inductor l/dcr time constant, then v c is equal to the voltage drop across the dcr multiplied by the ratio of the resistor divider, k. if a resistor divider is not being used, the value for k is 1 . the capacitor voltage v c , is then replicated across the sense resistor r isen . the regulator should have only one r isen resistor connected from the v out plane to the icommon pin . the current through r isen is proportional to the inductor current. equation 9 shows that the proportion between the channel current and the sensed current (i sen ) is driven by the value of the sense resistor chosen, the resistor divider ratio, and the dcr of the inductor. channel-current balance the sampled currents, i n , from each active channel are summed together and divided by the number of active channels. the resulting cycle average current, i avg , provides a measure of the to tal load-current demand on the converter during each switching cycle. channel-current balance is achieved by comparing the sampled current of each channel to the cycle average current, and making the proper adjustment to each channel pulse width based on the error. intersil?s patent ed current-balance method is illustrated in figure 6, with error correction for channel 1 represented. in the figure, the cycle average current combines with the channel 1 sample, i 1 , to create an error signal i er . figure 4. isl6565a internal and external current- sensing circuitry i n i sen i l r ds on () r isen ------------------------- - = - + isen(n) r isen sample & hold isl6565a internal circuit external circuit v in channel n upper mosfet channel n lower mosfet - + i l r ds on () i l v l s () i l sl dcr + ? () ? = (eq. 5) v c s () sl ? dcr ------------- 1 + ?? ?? sr 1 c ?? 1 + () ------------------------------------- - dcr i l ? ? = (eq. 6) v c s () sl ? dcr ------------- 1 + ?? ?? s r 1 r 2 ? () r 1 r 2 + ----------------------- - c ?? 1 + ?? ?? ?? ------------------------------------------------------- - kdcri l ?? ? = (eq. 7) k r 2 r 2 r 1 + -------------------- - = (eq. 8) figure 5. dcr sensing configuration i n - + isen(n) sample & hold ISL6565B internal circuit v in icommon pwm(n) isl6605 r isen dcr l inductor r 1 v out c out - + v c (s) c i l - + v l (s) i sen r 2* v c (s) + - *r 2 is optional i n ki l dcr r isen ----------------- - ?? = (eq. 9) isl6565a, ISL6565B
13 the filtered error signal modifies the pulse width commanded by v comp to correct any unbalance and force i er toward zero. the same method for error signal correction is applied to each active channel. channel-current balance is essent ial in realizing the thermal advantage of multi-phase operat ion. the heat generated in conversion is dissipated over multiple devices and a large area. the designer avoids the co mplexity of driving multiple parallel mosfets, and the expense of using heat sinks and non-standard magnetic materials. voltage regulation the integrating compensation network shown in figure 7 insures that the steady-state error in the output voltage is limited only to the error in t he reference voltage (output of the dac) and offset errors in the ofs current source, remote-sense and error amplifiers. intersil specifies the guaranteed tolerance of the isl6565a, ISL6565B to include the combined tolerances of each of these elements. the output of the error amplifier, v comp , is compared to the sawtooth waveform to generate the pwm signals. the pwm signals control the timing of the intersil mosfet drivers and regulate the converter output to the specified reference voltage. the internal and external circuitry that controls voltage regulation is illustrated in figure 7. the isl6565 incorporates an internal differential remote- sense amplifier in the feedback path. the amplifier removes the voltage error encountered when measuring the output voltage relative to the controller ground reference point resulting in a more accurate means of sensing output voltage. connect the microprocessor sense pins to the non- inverting input, vsen, and in verting input, rgnd, of the remote-sense amplifier. the remote-sense output, v diff , is connected to the inverting input of the error amplifier through an external resistor. a digital to analog converter (dac) generates a reference voltage based on the state of logic signals at pins vid4 through vid12.5. the dac decodes the 6-bit logic signal (vid) into one of the discrete voltages shown in table 1. each vid input offers a 20 a pull-up to an internal 2.5v source for use with open-drain outputs. the pull-up current diminishes to zero above the logic threshold to protect voltage-sensitive output device s. external pull-up resistors can augment the pull-up current sources in case leakage into the driving device is greater than 20 a. figure 6. channel-1 pwm function and current- balance adjustment n i avg i 3 * i 2 - + + - + - f(s) pwm1 i 1 v comp sawtooth signal i er note: *channel 3 is optional. filter figure 7. output voltage and load-line regulation with offset adujustment i avg external circuit isl6565 internal circuit comp r c r fb fb vdiff vsen rgnd - + v droop error amplifier - + v out + differential remote-sense amplifier v comp c c ref r tcomp c ref - + v out - vid dac 1k isl6565a, ISL6565B
14 load-line regulation some microprocessor manufacturers require a precisely- controlled output impedance. this dependence of output voltage on load current is often termed ?droop? or ?load line? regulation. table 1. voltage identification (vid) codes vid4 vid3 vid2 vid1 vid0 vid12.5 vdac 0 1 0 1 0 0 0.8375v 0 1 0 0 1 1 0.8500v 0 1 0 0 1 0 0.8625v 0 1 0 0 0 1 0.8750v 0 1 0 0 0 0 0.8875v 0 0 1 1 1 1 0.9000v 0 0 1 1 1 0 0.9125v 0 0 1 1 0 1 0.9250v 0 0 1 1 0 0 0.9375v 0 0 1 0 1 1 0.9500v 0 0 1 0 1 0 0.9625v 0 0 1 0 0 1 0.975v0 0 0 1 0 0 0 0.9875v 0 0 0 1 1 1 1.0000v 0 0 0 1 1 0 1.0125v 0 0 0 1 0 1 1.0250v 0 0 0 1 0 0 1.0375v 0 0 0 0 1 1 1.0500v 0 0 0 0 1 0 1.0625v 0 0 0 0 0 1 1.0750v 0 0 0 0 0 0 1.0875v 1111 1 1 off 1111 1 0 off 1 1 1 1 0 1 1.1000v 1 1 1 1 0 0 1.1125v 1 1 1 0 1 1 1.1250v 1 1 1 0 1 0 1.1375v 1 1 1 0 0 1 1.1500v 1 1 1 0 0 0 1.1625v 1 1 0 1 1 1 1.1750v 1 1 0 1 1 0 1.1875v 1 1 0 1 0 1 1.2000v 1 1 0 1 0 0 1.2125v 1 1 0 0 1 1 1.2250v 1 1 0 0 1 0 1.2475v 1 1 0 0 0 1 1.2500v 1 1 0 0 0 0 1.2625v 1 0 1 1 1 1 1.2750v 1 0 1 1 1 0 1.2875v 1 0 1 1 0 1 1.3000v 1 0 1 1 0 0 1.3125v 1 0 1 0 1 1 1.3250v 1 0 1 0 1 0 1.3375v 1 0 1 0 0 1 1.3500v 1 0 1 0 0 0 1.3625v 1 0 0 1 1 1 1.3750v 1 0 0 1 1 0 1.3875v 1 0 0 1 0 1 1.4000v 1 0 0 1 0 0 1.4125v 1 0 0 0 1 1 1.4250v 1 0 0 0 1 0 1.4375v 1 0 0 0 0 1 1.4500v 1 0 0 0 0 0 1.4625v 0 1 1 1 1 1 1.4750v 0 1 1 1 1 0 1.4875v 0 1 1 1 0 1 1.5000v 0 1 1 1 0 0 1.5125v 0 1 1 0 1 1 1.5250v 0 1 1 0 1 0 1.5375v 0 1 1 0 0 1 1.5500v 0 1 1 0 0 0 1.5625v 0 1 0 1 1 1 1.5750v 0 1 0 1 1 0 1.5875v 0 1 0 1 0 1 1.600v table 1. voltage identificati on (vid) codes (continued) vid4 vid3 vid2 vid1 vid0 vid12.5 vdac isl6565a, ISL6565B
15 as shown in figure 7, a current proportional to the average current in all active channels, i avg , flows from fb through a load-line regulation resistor, r fb . the resulting voltage drop across r fb is proportional to the output current, effectively creating an output voltage droo p with a steady-state value defined as in most cases, each channel uses the same component values to sense current. if this is the case you can derive a more complete equation for v droop for each current sense method being used. output-voltage offset programming the isl6565a, ISL6565B allows the designer to accurately adjust the offset voltage by connecting a resistor, r ofs , from the ofs pin to vcc or gnd. when r ofs is connected between ofs and vcc, the voltag e across it is regulated to 2.0v. this causes a proportional current (i ofs ) to flow into the ofs pin and out of the fb pin. if r ofs is connected to ground, the voltage across it is regulated to 0.5v, and i ofs flows into the fb pin and out of the ofs pin. the offset current flowing through the resistor between vdiff and fb will generate the desired offset voltage which is equal to the product (i ofs x r fb ). these functions are shown in figures 8 and 9. once the desired output offset voltage has been determined, use the following formulas to set r ofs : for positive offset (connect r ofs to gnd): for negative offset (connect r ofs to vcc): dynamic vid modern microprocessors need to make changes to their core voltage as part of normal operation. they direct the core- voltage regulator to do this by making changes to the vid inputs. the core-voltage regulator is required to monitor the dac inputs and respond to on-the-fly vid changes in a controlled manner supervising a safe output voltage transition without discontinuity or disruption. v droop i avg r fb = (eq. 10) v droop i out n ------------- r ds on () r isen ---------------------- r fb = (eq. 11) (isl6565a only) r ds(on) sensing v droop i out n ------------- k dcr r isen ----------------- - r fb ?? = (eq. 12) (ISL6565B only) dcr sensing (eq. 13) r ofs 0.5 r fb v offset -------------------------- = (eq. 14) r ofs 2r fb v offset -------------------------- = e/a fb ofs vcc gnd + - + - 0.5v 2.0v gnd r ofs r fb vdiff isl6565a, ISL6565B figure 8. positive offset output voltage programming vref v ofs + - i ofs e/a fb ofs vcc gnd + - + - 0.5v 2.0v vcc r ofs r fb vdiff isl6565a, ISL6565B figure 9. negative offset output voltage programming vref v ofs + - i ofs isl6565a, ISL6565B
16 the isl6565a, ISL6565B checks the vid inputs six times every switching cycle. if the vid code is f ound to have changed, the controller waits ha lf of a complete cycle before executing a 12.5mv change. if during the half-cycle wait period, the difference between the dac level and the new vid code changes sign, no change is made. if the vid code is more than 1 bit higher or lower than the dac (not recommended), the controller will execute 12.5mv changes six times per cycle until vid and dac are equal. it is important to carefully control the rate of vid stepping in 1-bit increments. in order to ensure the smooth transition of output voltage during vid change, a vid step change smoothing network is required for an isl6565a, ISL6565B based voltage regulator. this network is composed of a 1k ? internal resistor between the output of dac and the capacitor c ref , between the ref pin and ground. the selection of c ref is based on the time duration for 1 bit vid change and the allowable delay time. assuming the microprocessor controls the vid change at 1 bit every t vid , the relationship between c ref and t vid is given by equation 15. as an example, for a vid step change rate of 5 s per bit, the value of c ref is 22nf based on equation 15. temperature compensation mosfet r ds(on) and inductor dcr are both susceptible to changes in value due to temp erature. since output voltage positioning is derived from the channel current sensed across these two elements, any variation in resistance results in a corresponding error in the output voltage. the temperature coefficient, , of the r ds(on) or dcr is the parameter that determines how much the resistance varies with temperature. as temperature increases above ambient, the average sensed current, i avg , changes in proportion to the temperature coefficient and temperature rise as shown in equation 16. with this resulting error, i avg can now be described as the sum of two parts, the average sensed current at ambient temperature and the resulting error current, i err , due to the temperature rise. in order to compensate for th is error current, the isl6565a, ISL6565B includes a temperature compensation circuit that injects a current, i tcomp , into the fb pin. this current is created by pushing the average sense current through a selectable external resistor, r tcomp . as shown in figure 10, the voltage drop developed across r tcomp is then sensed and multiplied by a known gain, k tc , which is determined by the internal ic temperature. this gain creates the temperature compensation current, i tcomp , that is injected into the fb pin. select r tcomp such that i tcomp equals i err over the entire range of operating temp erature. the resulting droop current accurately represents the load current; achieving a linear, temperature-independant load line. initialization prior to initialization, proper conditions must exist on the enable inputs and vcc. when the conditions are met, the controller begins soft-start. once the output voltage is within the proper window of operation, the controller asserts pgood. enable and disable while in shutdown mode, the pwm outputs are held in a high-impedance state to assure the drivers remain off. the following input conditions must be met before the isl6565a, ISL6565B is released from shutdown mode. 1. the bias voltage applied at vcc must reach the internal power-on reset (por) rising threshold. once this threshold is reached, proper operation of all aspects of the isl6565a, ISL6565B is guaranteed. hysteresis between the rising and falling thresholds assure that once enabled, the isl6565a, ISL6565B will not inadvertently turn off unless the bias voltage drops substantially (see electrical specifications ). c ref 0.004x t vid = (eq. 15) i avg i avg t ambient () 1 tt ambient ? () + [] ? = (eq. 16) i err t () i avg t ambient () tt ambient ? () ?? = (eq. 17) fb r fb isl6565a, ISL6565B figure 10. temperature compensation circuitry v droop + - k tc r tcomp tcomp i avg i avg i tcomp vdiff i droop i tcomp k tc t25 ? () i avg r tcomp ??? = (eq. 18) isl6565a, ISL6565B
17 2. the voltage on en must be above 1.31v. the en input allows for power sequencing between the controller bias voltage and another voltage rail. the enable comparator holds the isl6565a, ISL6565B in shutdown until the voltage at en rises above 1.31v. the enable comparator has about 100mv of hysteresis to prevent bounce. it is important that the driver ic s reach their por level before the isl6565a, ISL6565B becomes enabled. the schematic in figure 11 dem onstrates sequencing the isl6565a, ISL6565B with the hip660x family of intersil mosfet drivers, which require 12v bias. 3. the voltage on enll must be logic high to enable the controller. this pin is ty pically connected to the vid_pgood. 4. the vid code must not be 111111 or 111110. these codes signal the controller that no l oad is present. the controller will enter shut-down mode after receiving either of these codes and will execute soft-start upon receiving any other code. these codes can be used to enable or disable the controller but it is not recommended. after receiving one of these codes, the controller executes a 2-cycle delay before changing the overvoltage trip level to the shut- down level and disabling pwm. overvoltage shutdown cannot be reset using one of these codes. when each of these conditions is true, the controller immediately begins the soft-start sequence. soft-start during soft-start, the dac volt age ramps linearly from zero to the programmed vid level. the pwm signals remain in the high-impedance state until the controller detects that the ramping dac level has reached the output-voltage level. this protects the system against the large, negative inductor currents that would otherwise occur when starting with a pre- existing charge on the output as the controller attempted to regulate to zero volts at the b eginning of the soft-start cycle. the soft-start time, t ss , begins with a delay period equal to 64 switching cycles followed by a linear ramp with a rate determined by the switching period, 1/f sw . for example, a regulator with a 250khz switching frequency, having vid set to 1.35v, has t ss equal to 6.912ms. a 100mv offset exists on the remote-sense amplifier at the beginning of soft-start and ramps to zero during the first 640 cycles of soft-start (704 cycl es following enable). this prevents the large inrush curre nt that would otherwise occur should the output voltage star t out with a slight negative bias. during the first 640 cycles of soft-start (704 cycles following enable) the dac voltage increments the reference in 25mv steps. the remainder of soft-start sees the dac ramping with 12.5mv steps. fault monitoring and protection the isl6565a, ISL6565B actively monitors output voltage and current to detect fault conditions. fault monitors trigger protective measures to prevent damage to a microprocessor load. one common power good indicator is provided for linking to external syst em monitors. the sc hematic in figure 13 outlines the interaction between the fault monitors and the power good signal. figure 11. power sequencing using threshold- sensitive enable (en) function - + 1.24v external circuit isl6565a, ISL6565B internal circuit en +12v por circuit 10.7k ? 1.40k ? enable comparator soft-start and fault logic enll vcc t ss 64 1280 vid ? + f sw ----------------------------------------- = (eq. 19) figure 12. soft-start waveforms with an un-biased output. fsw = 500khz vout, 500mv/div en, 5v/div 500ms/div 2ms/div isl6565a, ISL6565B
18 power good signal the power good pin (pgood) is an open-drain logic output that transitions high when t he converter is operating after soft-start. pgood pulls low during shutdown and releases high after a successful soft-start. pgood only transitions low when an undervoltage condition is detected or the controller is disabled by a reset from en, enll, por, or one of the no-cpu vid codes. after an undervoltage event, pgood will return high unless the controller has been disabled. pgood does not auto matically transition low upon detection of an overvoltage condition. undervoltage detection the undervoltage threshold is set at 75% of the vid code. when the output vo ltage at vsen is bel ow the undervoltage threshold, pgood gets pulled low. no other action is taken by the controller. overvoltage protection when vcc is above 1.4v, but otherwise not valid as defined under power on reset in electrical specifications , the overvoltage trip circuit is active using auxiliary circuitry. in this state, an overvo ltage trip occurs if the voltage at vsen exceeds 1.8v. with valid vcc, the overvolta ge circuit is sensitive to the voltage at vdiff. in this state, the trip level is 1.7v prior to valid enable conditions being met as described in enable and disable . the only exception to this is when the ic has been disabled by an overvoltage trip. in that case the overvoltage trip point is vid plus 200mv. during soft-start, the overvoltage trip level is th e higher of 1.7v or vid plus 200mv. upon successful soft-start, the overvoltage trip level is 200mv above vid. two ac tions are taken by the isl6565a, ISL6565B to protect the microprocessor load when an overvoltage condition occurs. at the inception of an overvo ltage event, all pwm outputs are commanded low until the voltage at vsen falls below 0.6v with valid vcc or 1.5v otherwise. this causes the intersil drivers to turn on the lower mosfets and pull the output voltage below a level that might cause damage to the load. the pwm outputs remain low until vdiff falls to the programmed dac level at which time they enter a high- impedance state. the intersil drivers respond to the high- impedance input by turning off both upper and lower mosfets. if the overvoltage condition reoccurs, the isl6565a, ISL6565B will again command the lower mosfets to turn on. the isl6565a, ISL6565B will continue to protect the load in this fash ion as long as the overvoltage condition recurs. simultaneous to the protective action of the pwm outputs, the ovp pin pulls to vcc delivering up to 100ma to the gate of a crowbar mosfet or scr placed ei ther on the input rail or the output rail. turning on the mosfet or scr collapses the power rail and causes a fuse pl aced further up stream to blow. the fuse must be sized such that the mosfet or scr will not overheat before the fuse blows. the ovp pin is tolerant to 12v (see absolute maximum ratings ), so an external resistor pull up can be used to augment the driving capability. if using a pull up resistor in conjunction with the internal overvoltage protection function, care must be taken to avoid nuisance trips that could occur when vcc is below 2v. in that case, the controller is incapable of holding ovp low. once an overvoltage condition is detected, normal pwm operation ceases until the isl6565a, ISL6565B is reset. cycling the voltage on en, enll, or vcc below the por- falling threshold will reset the controller. cycling the vid codes will not reset the controller. overcurrent protection isl6565a, ISL6565B has two levels of overcurrent protection. each phase is protected from a sustained overcurrent condition on a delayed basis, while the combined phase currents are protected on an instantaneous basis. in instantaneous protection m ode, the isl6565a, ISL6565B takes advantage of the proportionality between the load current and the average current, i avg , to detect an overcurrent condition. see the channel-current balance section for more detail on how the average current is measured. the average current is continually compared with a constant 110 a reference current as shown in figure 6. once the average current exceeds the reference current, a comparator triggers the converter to shutdown. in individual overcurrent pr otection mode, the isl6565a, ISL6565B continuously compares the current of each channel with the same 110 a reference current. if any channel current exceeds the reference current continuously for eight figure 13. power good and protection circuitry ovp - + vid + 0.2v vdiff - + 110 a i avg - + dac reference ov oc uv pgood 75% soft-start, fault and control logic - + oc i 1 repeat for each channel 110 a isl6565a, ISL6565B
19 consecutive cycles, the comparat or triggers the converter to shutdown. at the beginning of overcurrent shutdown, the controller places all pwm signals in a high-impedance state commanding the intersil mosfet driver ics to turn off both upper and lower mosfets. the system remains in this state for a period of 4096 sw itching cycles. if the controller is still enabled at the end of this wait period, it will attempt a soft- start (as shown in figure 14). if the fault remains, the trip- retry cycles will continue indefinite ly until either the controller is disabled or the fault is cl eared. note that the energy delivered during trip-retry cycling is much less than during full-load operation, so there is no thermal hazard. general design guide this design guide is intended to provide a high-level explanation of the steps necessa ry to create a multi-phase power converter. it is assumed that the reader is familiar with many of the basic skills and techniques referenced below. in addition to this guide, intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for all common microprocessor applications. power stages the first step in designing a multi-phase converter is to determine the number of phases. this determination depends heavily on the cost analysis which in turn depends on system constraints that differ from one design to the next. principally, the designer will be concerned with whether components can be mounted on both sides of the circuit board, whether through-hole components are permitted, the total board space available for power-supply circuitry, and the maximum amount of load current. generally speaking, the most economical soluti ons are those in which each phase handles between 25 and 30a. all surface-mount designs will tend toward the lower end of this current range. if through-hole mosfets and inductors can be used, higher per-phase currents are possible. in cases where board space is the limiting constraint, current can be pushed as high as 40a per phase, but thes e designs require heat sinks and forced air to cool the mosfets, inductors and heat- dissipating surfaces. mosfets the choice of mosfets depends on the current each mosfet will be required to con duct, the switching frequency, the capability of the mosfets to dissipate heat, and the availability and nature of heat sinking and air flow. lower mosfet power calculation the calculation for power loss in the lower mosfet is simple, since virtually all of the loss in the lower mosfet is due to current conducted through the channel resistance (r ds(on) ). in equation 20, i m is the maximum continuous output current, i pp is the peak-to-peak inductor current (see equation 1), and d is the duty cycle (v out /v in ). an additional term can be added to the lower-mosfet loss equation to account for additional loss accrued during the dead time when inductor current is flowing through the lower-mosfet body diode. this term is dependent on the diode forward voltage at i m , v d(on) , the switching frequency, f s , and the length of dead times, t d1 and t d2 , at the beginning and the end of the lower-mosfet conduction interval respectively. the total maximum power dissipated in each lower mosfet is approximated by the summation of p low,1 and p low,2 . upper mosfet power calculation in addition to r ds(on) losses, a large portion of the upper- mosfet losses are due to currents conducted across the input voltage (v in ) during switching. since a substantially higher portion of the upper-mosfet losses are dependent on switching frequency, the power calculation is more complex. upper mosfet losses can be divided into separate components involving the upper-mosfet switching times, the lower-mosfet body-diode reverse- recovery charge, q rr , and the upper mosfet r ds(on) conduction loss. when the upper mosfet turns of f, the lower mosfet does not conduct any portion of th e inductor current until the voltage at the phase node falls below ground. once the lower mosfet begins conducting, the current in the upper mosfet falls to zero as the current in the lower mosfet ramps up to assume the full inductor current. in equation 22, 0a 0v 2ms/div output current, 50a/div figure 14. overcurrent behavior in hiccup mode f sw = 500khz output voltage, 500mv/div p low 1 , r ds on () i m n ----- - ?? ?? ?? 2 1d ? () i lpp , 2 1d ? () 12 -------------------------------- + = (eq. 20) p low 2 , v don () f s i m n ----- - i pp 2 -------- - + ?? ?? t d1 i m n ----- - i pp 2 -------- - ? ?? ?? ?? t d2 + = (eq. 21) isl6565a, ISL6565B
20 the required time for this commutation is t 1 and the approximated associated power loss is p up,1 . at turn on, the upper mosfet begins to conduct and this transition occurs over a time t 2 . in equation 23, the approximate power loss is p up,2 . a third component involves the lower mosfet?s reverse- recovery charge, q rr . since the inductor current has fully commutated to the upper mosfet before the lower- mosfet?s body diode can recover all of q rr , it is conducted through the upper mosfet across vin. the power dissipated as a result is p up,3 . finally, the resistive part of the upper mosfets is given in equation 25 as p up,4 . the total power dissipated by the upper mosfet at full load can now be approximated as the summation of the results from equations 22, 23, 24 and 25. since the power equations depend on mosfet parameters, choosing the correct mosfets can be an it erative process involving repetitive solutions to the loss equations for different mosfets and different switching frequencies. current sensing component selection the isl6565a supports mosfet r ds(on) current sensing, while the ISL6565B uses inductor dcr current sensing. the procedures for choosing the components for each method of current sensing are very different and are described in the next two sections. mosfet r ds(on) sensing (isl6565a only) the isl6565a senses the channel load current by sampling the voltage across the lower mosfet r ds(on) , as shown in figure 15. the isen pins are denoted isen1, isen2, and isen3. the resistors connected between these pins and the respective phase nodes determine the gains in the load-line regulation loop and the channel-current balance loop as well as setting the overcurrent trip point. select values for these resistors based on the room temperature r ds(on) of the lower mosfets; the full-load operating current, i fl ; and the number of phases, n using equation 26. in certain circumstances, it ma y be necessary to adjust the value of one or more isen resistor. when the components of one or more channels are inhibited from effectively dissipating their heat so that the affected channels run hotter than desired, choose new, smaller values of r isen for the affected phases (see the section entitled voltage regulation ). choose r isen,2 in proportion to the desired decrease in temperature rise in order to cause proportionally less current to flow in the hotter phase. in equation 27, make sure that ? t 2 is the desired temperature rise above the ambient temperature, and ? t 1 is the measured temperature rise above the am bient temperature. while a single adjustment according to equation 27 is usually sufficient, it may occasionally be necessary to adjust r isen two or more times to achieve optimal thermal balance between all channels. inductor dcr sensing (ISL6565B only) the ISL6565B senses the channel load current by sampling the voltage across the output inductor dcr, as described in the current sensing section. as figure 16 illustrates, an r-c network across the inductor is required to sense the channel current accurately. p up 1 , v in i m n ----- - i pp 2 -------- - + ?? ?? t 1 2 ---- ?? ?? ?? f s (eq. 22) p up 2 , v in i m n ----- - i pp 2 -------- - ? ?? ?? t 2 2 ---- ?? ?? ?? f s (eq. 23) p up 2 , v in i m n ----- - i pp 2 -------- - ? ?? ?? t 2 2 ---- ?? ?? ?? f s p up 3 , v in q rr f s = (eq. 24) p up 4 , r ds on () i m n ----- - ?? ?? ?? 2 d i pp 2 12 --------- - + (eq. 25) figure 15. isl6565a internal and external current- sensing circuitry isen(n) r isen v in channel n upper mosfet channel n lower mosfet - + i l r ds on () i l isl6565a r isen r ds on () 70 10 6 ? ----------------------- i fl n ------- - = (eq. 26) r isen 2 , r isen ? t 2 ? t 1 ---------- = (eq. 27) isl6565a, ISL6565B
21 the time constant of this r-c network must match the time constant of the inductor l/dcr. follow the steps below to choose the component values for this r-c network. 1. choose an arbitrary value for c. the recommended value is 0.01 f. 2. plug the inductor l and dcr component values, and the values for c chosen in steps 1, into equation 28 to calculate your value for r 1 . do not populate r 2 . due to errors in the inductance or dcr it may be necessary to adjust the value of r 1 for each phase to match the time constants correctly. once the r-c network components have been chosen, use equation 29 to calculate the value of r isen . in equation 29, dcr is the dcr of the output indu ctor at room temperature, i fl is the full load operating current, and n is the number of phases. adjusting phase currents (ISL6565B only) layout issues in the core-power regulator may cause the currents in each phase to be slightly unbalanced. this problem can be resolved without any changes to the layout or any significant cost increase. the solution requires populating r 2 in certain phases (as shown in figure 16) to create a resistor divider ratio, k, for each phase. the time constant of each new resistor divider r-c sense network must match the time constant of the old sense network. follow the steps below to choose the component values for the resistor divider r-c network for each phase. 1. load the regulator to full l oad and allow the board to heat until the output voltage st abilizes (usually several minutes). 2. measure the current flowing through each phase, labeling the highest phase current, i high , and the other, lower phase currents i low (1) and i low (2). 3. individually, plug the values for each low phase current, i low (n), the highest phase current, i high , the full load current, i load , and the number of phases, n, into equation 30 to calculate the resistor divider ratio, k low , for each low phase. (note: the phase with the highest phase current is the referenc e phase and it will not use a resistor divider network, keep ing its resistor divider ratio equal to 1.) 4. for each phase, calculate the values for the new r-c network sense resistors, r 1,new and r 2,new , by plugging in each phase?s new resistor divider ratio, k low , and each phase?s present sense resistor r 1 , into equations 31 and 32. after calculating the new resistor divider sense resistors, the phases will be balanced. it may be necessary to adjust the r isen resistor slightly to correct for any changes in the desired i sen current that results from adding the resistor dividers. the phase currents might also have to be adjusted if the components of one or more phases are inhibited from effectively dissipating their heat so that the affected phases run hotter than desired. in this case it may be necessary to adjust the resistor divider ratio of one or more of the r-c networks. doing so adjusts the current through affected phases and can balance the te mperatures of each phase. choose r 1,new and r 2,new in relation to the desired change in temperature, as described in equations 33 and 34, in order to cause less current to flow in the hotter phase. in equations 33 and 34, ? t 2 is the desired temperature rise above the ambient temperature, and ? t 1 is the measured temperature rise above the ambient temperature. it is figure 16. dcr sensing configuration isen(n) ISL6565B v in icommon pwm(n) isl6605 r isen dcr l inductor r 1 v out c out - + v c (s) c i l - + v l (s) i sen r 2 r 1 l dcr c ? ---------------------- = (eq. 28) r isen dcr i fl ? 70 10 6 ? n ? --------------------------------- - = (eq. 29) k low n () 1 i low n () i high ? i load n ? --------------------------------------------- + = (eq. 30) r 1new , n () r 1 n () k low n () ------------------------- = (eq. 31) r 2new , n () r 1 n () 1k ? low n () ---------------------------------- - = (eq. 32) r 1 new , r 1 ? t 2 ? t 1 ---------- = (eq. 33) r 2 new , r 1 r 2 ? r 1 r 2 1 t 1 ? t 2 ? --------- - ? ?? ?? ?? ? + -------------------------------------------------- - = (eq. 34) isl6565a, ISL6565B
22 important to note that when using equations 33 and 34 the resistor divider ratio of the corresponding phase rc network is being changed. in the phase being adjusted, this new ratio, k new (described in equation 32), can not exceed 1.0. if this occurs, the current in the hot phase cannot be reduced any more. instead of decreasing the current in the hot phase, the current must be increased in the colder phases. to accomplish this, use equations 33 and 34 to get the desired temperature rise in the cold phases. while a single adjustment, according to equations 33 and 34, is usually sufficient, it may oc casionally be necessary to adjust r 1 and r 2 in the corresponding channels two or more times to achieve optimal thermal balance between all phases. load-line regulation resistor the load-line regulation resistor is labeled r fb in figure 7. its value depends on the desired full-load droop voltage (v droop in figure 7). once the isen resistor has been chosen, the load-line regulation resistor can be calculated using equation 36. if one or more of the isen re sistors is adjusted for thermal balance, as in equation 26, the load-line regulation resistor should be selected according to equation 37 where i fl is the full-load operating current and r isen(n) is the isen resistor connected to the n th isen pin. temperature compensation resistor by combining equations 17 and 18 found in the temperature compensation section, the value of the tcomp resistor can be determined using equation 38. in equation 38, k t is the temperature coupling coefficient between the isl6565a and the closest lower mosfet, or the ISL6565B and the output inductor. it represents how closely the controller temperature tracks the lower mosfet or inductor temperature. the value of k t is typically between 75% and 100%. k tc is the temperature dependant transconductance of the intern al compensation circuit. its value is designed as 2 a/v/c. the temperature coefficient of mosfet r ds(on) or inductor dcr is given by . this is the ratio of the change in resistance to the change in temperature. resistance is normalized to the value at 25c and the value of is typically between 0.35%/c and 0.50%/c. according to equation 38, a voltage regulator with 80% thermal coupling coefficient between the controller and lower mosfet and 0.4%/c temperature coefficient of mosfet r ds(on) requires a 2.5k ? tcomp resistor. if the exact value for k t and are not known, equation 38 can give an incorrect value for r tcomp . if this is the case, follow the steps below to obtain an accurate value for r tcomp . this procedure works by making two output voltage measurements. the first is made by using too much temperature compensation, and the second with too little. each of the measurements produces an error and a linear interpolation is used to find a tcomp resistor value to produce zero error. make all measurements using a digital multimeter accurate to 100 v or better. 1. install a 5k ? resistor (r 1 ) for r tcomp . 2. start the regulator at room temperature and apply full load current. record the output voltage, v 1 , immediately after loading the regulator. 3. allow the board to heat until the output voltage stabilizes (usually several minutes). record the output voltage, v 2 . 4. install a 1k ? resistor (r 2 ) for r tcomp . 5. start the regulator at room temperature and apply full load current. record the output voltage, v 3 , immediately after loading the regulator. 6. allow the board to heat until the output voltage stabilizes (usually several minutes). record the output voltage, v 4 . 7. calculate the correct value for r tcomp using equation 39. compensation the two opposing goals of compensating the voltage regulator are stability and speed. the load-line regulated converter behaves in a similar manner to a peak-current mo de controller because the two poles at the output-filter l- c resonant frequency split with the introduction of current information into the control loop. the final location of these poles is determined by the system function, the gain of the current signal, and the value of the compensation components, r c and c c . k new k ? t 1 ? t 2 ---------- = (eq. 35) r fb v droop 70 10 6 ? ------------------------ - = (eq. 36) r fb v droop i fl r ds on () -------------------------------- r isen n () n = (eq. 37) (eq. 38) r tcomp k t k tc --------------------- - = (eq. 39) r tcomp r 1 r 1 r 2 ? () v 2 v 1 ? () v 2 v 1 ? () v 3 v 4 ? () + -------------------------------------------------------- ? = isl6565a, ISL6565B
23 since the system poles and zero are affected by the values of the components that are meant to compensate them, the solution to the system equatio n becomes fairly complicated. fortunately, there is a simple approximation that comes very close to an optimal solution. tr eating the system as though it were a voltage-mode regulator, by compensating the l-c poles and the esr zero of the voltage-mode approximation, yields a solution that is always stable with very close to ideal transient performance. select a target bandwidth fo r the compensated system, f 0 . the target bandwidth must be large enough to assure adequate transient performance, but smaller than 1/3 of the per-channel switching frequency. the values of the compensation components depend on the relationships of f 0 to the l-c pole frequency and the esr zero frequency. for each of the following three, there is a separate set of equations for the compensation components. . in equations 40, l is the per-channel filter inductance divided by the number of active channels; c is the sum total of all output capacitors; esr is the equivalent-series resistance of the bulk output -filter capacitance; and v pp is the peak-to-peak sawtooth signal amplitude as described in figure 6 and electrical specifications . once selected, the compensation values in equations 40 assure a stable converter with reasonable transient performance. in mo st cases, transient performance can be improved by making adjustments to r c . slowly increase the value of r c while observing the transient performance on an oscilloscope until no further improvement is noted. normally, c c will not need adjustment. keep the value of c c from equations 40 unless some performance issue is noted. the optional capacitor c 2 , is sometimes needed to bypass noise away from the pwm comparator (see figure 17). keep a position available for c 2 , and be prepared to install a high- frequency capacitor of between 22pf and 150pf in case any leading-edge jitter problem is noted. output filter design the output inductors and the ou tput capacitor bank together to form a low-pass filter responsible for smoothing the pulsating voltage at the phase nodes. the output filter also must provide the transient en ergy until the regulator can respond. because it has a low bandwidth compared to the switching frequency, the output filter limits the system transient response. the output capacitors must supply or sink load current while the current in the output inductors increases or decreases to meet the demand. in high-speed converters, the out put capacitor bank is usually the most costly (and often the largest) part of the circuit. output filter design begins with minimizing the cost of this part of the circuit. the critical load parameters in choosing the output capacitors are the maximum size of the load step, ? i, the load-current slew rate, di/dt, and the maximum allowable output-voltage deviation under transient loading, ? v max . capacitors are characterized according to their capacitance, esr, and esl (equivalent series inductance). at the beginning of the load tr ansient, the output capacitors supply all of the transient cu rrent. the output voltage will initially deviate by an amount approximated by the voltage drop across the esl. as the load current increases, the voltage drop across the esr increases linearly until the load current reaches its final value. the capacitors selected must figure 17. compensation configuration for load-line regulated isl6565a, ISL6565B circuit isl6565a, ISL6565B comp c c r c r fb fb vdiff - + v droop c 2 (optional) 1 2 lc ------------------- f 0 > r c r fb 2 f 0 v pp lc 0.75v in ----------------------------------- - = c c 0.75v in 2 v pp r fb f 0 ------------------------------------ = case 1: 1 2 lc ------------------- f 0 1 2 c esr () ----------------------------- - < r c r fb v pp 2 () 2 f 0 2 lc 0.75 v in -------------------------------------------- = c c 0.75v in 2 () 2 f 0 2 v pp r fb lc ------------------------------------------------------------- = case 2: (eq. 40) f 0 1 2 c esr () ----------------------------- - > r c r fb 2 f 0 v pp l 0.75 v in esr () ----------------------------------------- - = c c 0.75v in esr () c 2 v pp r fb f 0 l ------------------------------------------------- = case 3: isl6565a, ISL6565B
24 have sufficiently low esl and esr so that the total output- voltage deviation is less than the allowable maximum. neglecting the contribution of i nductor current and regulator response, the output voltage initially deviates by an amount the filter capacitor must have sufficiently low esl and esr so that ? v < ? v max . most capacitor solutions rely on a mixture of high-frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but limited high-frequency performance. minimizing the esl of the high-frequency capacitors allows them to support the output voltage as the current increases. minimizing the esr of the bulk capacitors allows them to supply the increased current with less output voltage deviation. the esr of the bulk capacitors also creates the majority of the output-voltage ripple. as the bulk capacitors sink and source the inductor ac ripple current (see interleaving and equation 2), a voltage develops across the bulk-capacitor esr equal to i c,pp (esr). thus, once the output capacitors are selected, the maximum allowable ripple voltage, v pp(max) , determines the lower limit on the inductance. since the capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. the output inductors must be capable of assuming the entire load current before the output voltage decreases more than ? v max . this places an upper limit on inductance. equation 43 gives the upper limit on l for the cases when the trailing edge of the current transient causes a greater output-voltage deviation than the leading edge. equation 44 addresses the leading edge. normally, the trailing edge dictates the selection of l because duty cycles are usually less than 50%. nevertheless, both inequalities should be evaluated, and l should be selected based on the lower of the two results. in each equation, l is the per-channel inductance, c is the total output capacitance, and n is the number of active channels. input supply voltage selection the vcc input of the isl6565 can be connected either directly to a +5v supply or thro ugh a current limiting resistor to a +12v supply. an integrated 5.8v shunt regulator maintains the voltage on the vcc pin when a +12v supply is used. a 300 ? resistor is suggested for limiting the current into the vcc pin to a worst-case maximum of approximately 25ma. switching frequency there are a number of variables to consider when choosing the switching frequency, as there are considerable effects on the upper-mosfet loss calcul ation. these effects are outlined in mosfets , and they establish the upper limit for the switching frequency. the lowe r limit is established by the requirement for fast transi ent response and small output- voltage ripple as outlined in output filter design . choose the lowest switching frequency that allows the regulator to meet the transient-response requirements. switching frequency is determi ned by the selection of the frequency-setting resistor, r t (see the figures labeled typical application on pages 5 and 6). figure 18 and equation 45 are provided to assist in selecting the correct value for r t . input capacitor selection the input capacitors are responsible for sourcing the ac component of the input curr ent flowing into the upper mosfets. their rms current capa city must be sufficient to handle the ac component of the current drawn by the upper mosfets which is related to duty cycle and the number of active phases. ? v esl () di dt ---- - esr ()? i + (eq. 41) l esr () v in nv out ? ?? ?? v out f s v in v pp max () ----------------------------------------------------------- - (eq. 42) l 2ncv o ? i () 2 --------------------- ? v max ? i esr () ? (eq. 43) l 1.25 () nc ? i () 2 ------------------------- - ? v max ? i esr () ? v in v o ? ?? ?? (eq. 44) r t 10 10.7 1.045 f s () log ? [] = (eq. 45) figure 18. r t vs switching frequency r t (k ? ) switching frequency (khz) 1000 100 10 10 100 1000 10000 isl6565a, ISL6565B
25 for a two-phase design, use figure 19 to determine the input-capacitor rms current requirement set by the duty cycle, maximum sustained output current (i o ), and the ratio of the peak-to-peak inductor current (i l,pp ) to i o . select a bulk capacitor with a ripple current rating which will minimize the total number of input capacitors required to support the rms current calculated. the voltage rating of the capacitors should also be at least 1.25 times greater than the maximum input voltage. figure 20 provides the same input rms current information for three phase designs respectively. use the same approach for selecting the bulk capacitor type and number. low capacitance, high-frequency ceramic capacitors are needed in addition to the input bulk capacitors to suppress leading and falling edge voltage spikes. the spikes result from the high current slew rate produced by the upper mosfet turn on and off. select low esl ceramic capacitors and place one as close as possible to each upper mosfet drain to minimize board parasitics and maximize suppression. figure 19. normalized input-capacitor rms current for 2-phase converter 0.3 0.1 0 0.2 input-capacitor current (i rms/ i o ) 00.4 1.0 0.2 0.6 0.8 duty cycle (v in/ v o ) i l,pp = 0 i l,pp = 0.5 i o i l,pp = 0.75 i o figure 20. normalized input-capacitor rms current for 3-phase converter duty cycle (v in/ v o ) 00.4 1.0 0.2 0.6 0.8 input-capacitor current (i rms/ i o ) 0.3 0.1 0 0.2 i l,pp = 0 i l,pp = 0.25 i o i l,pp = 0.5 i o i l,pp = 0.75 i o isl6565a, ISL6565B
26 isl6565a, ISL6565B quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) index d1/2 d1 d/2 d e1/2 e/2 e a 2x 0.15 b c 0.10 b a mc a n seating plane n 6 3 2 2 3 e 1 1 0.08 for odd terminal/side for even terminal/side c c section "c-c" nx b a1 c 2x c 0.15 0.15 2x b 0 ref. (nd-1)xe (ne-1)xe ref. 5 a1 4x p a c c 4x p b 2x a c 0.15 a2 a3 d2 d2 e2 e2/2 terminal tip side view top view 7 bottom view 7 5 c l c l e e e1 2 nx k nx b 8 nx l 8 8 9 area 9 4x 0.10 c / / 9 (datum b) (datum a) area index 6 area n 9 corner option 4x l1 l 10 l1 l 10 l28.5x5 28 lead quad flat no-lead plastic package (compliant to jedec mo-220vhhd-1 issue c) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.18 0.23 0.30 5,8 d 5.00 bsc - d1 4.75 bsc 9 d2 2.95 3.10 3.25 7,8 e 5.00 bsc - e1 4.75 bsc 9 e2 2.95 3.10 3.25 7,8 e 0.50 bsc - k0.25 - - - l 0.50 0.60 0.75 8 l1 - - 0.15 10 n282 nd 7 3 ne 8 7 3 p- -0.609 --129 rev. 0 02/03 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millim eters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.
27 isl6565a, ISL6565B small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mo ld flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. in- terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional . if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimen- sions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m28.3 (jedec ms-013-ae issue c ) 28 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.0200 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.6969 0.7125 17.70 18.10 3 e 0.2914 0.2992 7.40 7.60 4 e 0.05 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.01 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n28 287 0 o 8 o 0 o 8 o - rev. 0 12/93
28 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com isl6565a, ISL6565B thin shrink small outlin e plastic packages (tssop) index area e1 d n 123 -b- 0.10(0.004) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) c e 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-153-ae, issue e. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dam bar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimen- sion at maximum material condition. minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. (angles in degrees) 0.05(0.002) m28.173 28 lead thin shrink small outline plastic package symbol inches millimeters notes min max min max a- 0.047 - 1.20 - a1 0.002 0.006 0.05 0.15 - a2 0.031 0.051 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - d 0.378 0.386 9.60 9.80 3 e1 0.169 0.177 4.30 4.50 4 e 0.026 bsc 0.65 bsc - e 0.246 0.256 6.25 6.50 - l 0.0177 0.0295 0.45 0.75 6 n28 287 0 o 8 o 0 o 8 o - rev. 0 6/98

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